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cm i 9739 integrated multi-channel ac?97 cmi9739/CMI9739A six channel audio codec preliminary specifications description and overview features ? intel ? ac?97(rev 2.2) compatible, meeting microsoft? s ? pc2001 requirements ? built-in earphone buf fer and internal pll, the latter saving additional crystal. ? earphone buf fer , optional on hp_out pins(9739) or line_hp_out pins(9739a). ? line-in/rear out share the same jack. ? center/bass share the mic jack. ? digital s/pdif in/out support ? 48 lqfp package. ? crl ? 3d: hr tf based ds3d compatible audio engine. ? eax ? 1.0 & 2.0 compatible. ? sensaura ? 3d audio enhancement (optional). ? 18-20bit dac interface for spdif i/o(ich4). universalit y cmi9739 is a 6ch ac97 codec, applicable for major mb chipset s of intel, vi a, ali, and sis. cmi97 39 is ideal for pc2001-compliant desktops, n o tebooks, a nd home entertainment pcs where high-quality audio is a must. 6ch playback the specially-designe d 6ch hardware architecture of cmi973 9 allows multi-channe l south bridge to playback 6ch audio. cost-effectiveness a s to the cost concern, cmi9739 int egrates the earphone buf fer , an alog cd dif f erentia l interface, a nd analog switch for re ar channel audio to line-in. besides, mic-in can share same jack with ce nter/bass output fo r traditional 3 jacks au dio port to output 6 channels au dio. cmi9739 also ha s b u ilt-in pll to save additional crystal. more audio option last but not least, cmi9739 provides hr tf 3 d audio which interface compatible with eax ? / a3d ? /directsound3d ? . in addition, it provides sensaura ? 3d audio o p tion. in t hat regard, the audio quality of cmi9739 is fabulous beyond general expectation. revision date: may 2002 v e r s i o n : 1 . 3 1 .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 pin descriptions cmi9739 pin # signal name pin # signal name 1 d v d d 1 2 5 a v d d 1 2 x t l _ i n 2 6 a v s s 1 3 x t l _ o u t 2 7 v r e f 4 d v s s 1 2 8 v r e f o u t 5 s d a t a _ o u t 2 9 xt a l s 0 6 b i t _ c l k 3 0 xt a l s 1 7 d v s s 2 3 1 hp_out_l 8 s d a t a _ i n 3 2 hp_out_r 9 d v d d 2 3 3 n c 1 0 s y n c 3 4 n c 1 1 r e s e t # 3 5 line_out_l 1 2 p c _ b e e p 3 6 line_out_r 1 3 n c 3 7 n c 1 4 a u x _ l 3 8 a v d d 2 1 5 a u x _ r 3 9 s _ o u t _ l 1 6 n c 4 0 n c 1 7 n c 4 1 s _ o u t _ r 1 8 c d _ l 4 2 a v s s 2 1 9 c d _ g n d 4 3 c e n t e r _ o u t 2 0 c d _ r 4 4 l f e _ o u t 2 1 m i c 1 4 5 h p _ o n / g p i o 0 2 2 m i c 2 4 6 x t l s e l / g p i o 1 2 3 l i n e _ i n _ l 4 7 e a p d / s p d i f i n 2 4 l i n e _ i n _ r 4 8 s p d i f o cmi9739-6ch revision date: may 2002 v e r s i o n : 1 . 3 2 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 CMI9739A pin # signal name pin # signal name 1 d v d d 1 2 5 a v d d 1 2 x t l _ i n 2 6 a v s s 1 3 x t l _ o u t 2 7 v r e f 4 d v s s 1 2 8 v r e f o u t 5 s d a t a _ o u t 2 9 xt a l s 0 6 b i t _ c l k 3 0 xt a l s 1 7 d v s s 2 3 1 line_out_l 8 s d a t a _ i n 3 2 line_out_r 9 d v d d 2 3 3 n c 1 0 s y n c 3 4 n c 1 1 r e s e t # 3 5 line_hp_out_l 1 2 p c _ b e e p 3 6 line_hp_out_r 1 3 n c 3 7 n c 1 4 a u x _ l 3 8 a v d d 2 1 5 a u x _ r 3 9 s _ o u t _ l 1 6 n c 4 0 n c 1 7 n c 4 1 s _ o u t _ r 1 8 c d _ l 4 2 a v s s 2 1 9 c d _ g n d 4 3 c e n t e r _ o u t 2 0 c d _ r 4 4 l f e _ o u t 2 1 m i c 1 4 5 h p _ o n / g p i o 0 2 2 m i c 2 4 6 x t l s e l / g p i o 1 2 3 l i n e _ i n _ l 4 7 e a p d / s p d i f i n 2 4 l i n e _ i n _ r 4 8 s p d i f o CMI9739A-6ch revision date: may 2002 v e r s i o n : 1 . 3 3 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 cmi9739 mixer is de signed accor d ing to the ac?97 spe c ificat ions, capable of managing the playback and recording of all digital and analog audio sources in pc environment. it includes: ? sy stem audio: digital pcm input and output for business, gaming, and multimedia applications . ? cd/dvd analog cd/dvd-rom redbook audio with internal connections to codec mixer ? mono microphone desktop or headset mic with programmable boost and gain ? speakerphone system mic & speakers for telephony , dsvd, and video conferencing. ? stereo line in analog external line level source from consumer audio, video cameras, etc ? aux/sy n th analog fm or wavetable synthesizer , or other internal sources. s o u r c e f u n c t i o n c o n n e c t i o n pc_beep pc beep pass through from pc beeper output mic1 desktop microphone from mic jack mic2 headset microphone from headset mic jack line_in external audio source from line in jack cd audio from cd-rom drive cable from cd-rom aux upgrade sy nth or other exter nal sources internal connector pcm out digital audio output from ac ' 97 controller ac-link mix out mix of all sources ac ?97 internal center_out c e n t e r out channel to output jack lf e_out low frequency ef fect out channel to output jack line_out stereo mix of all sour ces (front channel) to output jack rear_out stereo output of rear (surround) channel to output jack hp_out stereo output w i th earphone buf fer (nc for 9739a) to output jack pcm in digital audio input to ac ' 97 controller ac-link output mix support : input mux support : ? s tereo mix of all sources for line _out ? any mono or stereo source ? s tereo output for rear_out ? m ono or stereo mix of all sources revision date: may 2002 v e r s i o n : 1 . 3 4 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 2. ordering informa t ion mode l numbe r package t e mperature range supply range cmi9739 48-pin lqf p 9mm 7mm 1.6mm 0 o c to + 70 o c dvdd = 3.3v , a v dd = 5v CMI9739A 48-pin lqf p 9mm 7mm 1.6 mm 0 o c to + 70 o c dvdd = 3.3v , a v dd = 5v outline of dimensions dimensions shown in inches and (mm ? 48-lead thin plastic quad flatpack (lqfp) (st-48) *c-media reserves the ri g ht to modif y the s p ecifications w i thout further notice. revision date: may 2002 v e r s i o n : 1 . 3 5 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 t able of contents 1. description and over view 1 2 . o r d e r i n g i n f o r m a t i o n 5 3 . p i n / s i g n a l d e s c r i p t i o n s 8 3 . 1 d i g i t a l i / o 8 3 . 2 a n a l o g i / o 8 3.3 fil t er and reference pins 9 3.4 power and ground signals 9 3 . 5 c o n f i g u r a t i o n s i g n a l s 9 3 . 6 s / p d i f s i g n a l s 9 4 . d i g i t a l i n t e r f a c e 1 0 4 . 1 a c _ l i n k 10 4 . 2 c l o c k i n g 10 4 . 3 r e s e t t i n g 10 4.4 ac-link digit a l serial interf ace prot ocol 11 4.5 ac-link audio input frame sda t a_in 12 4.6 ac-link audio output frame sda t a_out 15 4 . 7 a c - l i n k l o w p o w e r m o d e 17 5. cmi9739 mixer 20 5 . 1 m i x e r i n p u t 20 5 . 2 m i x e r o u t p u t 21 6 . r e g i s t e r i n t e r f a c e 2 2 6 . 1 r e g i s t e r d e s c r i p t i o n s 24 6 . 2 p i n d e s c r i p t i o n s 36 7. ac-link timing characteristics 38 7.1 cold reset 38 7.2 w a rm reset 38 7 . 3 c l o c k s 39 7 . 4 d a t a s e t u p a n d h o l d 40 7.5 signal rise and f a ll times 40 7.6 ac-link low power mode timing 41 7 . 7 a t e t e s t m o d e 42 8 . r e l e a s e n o t e 4 3 9 . r e f e r e n c e s 4 4 revision date: may 2002 v e r s i o n : 1 . 3 6 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 10. list of figures figure 1. ac ?97 connection to its companion controller 10 figure 2. ac ?97 standard bi-directional audio frame 11 figure 3. ac-link audio input frame 13 figure 4. start of an audio input frame 13 figure 5. ac-link audio output frame 15 figure 6. start of an audio output frame 15 figure 7. ac-link powerdown t i ming 18 figure 8. cold reset t i ming diagram 38 f i g u r e 9 . w a r m r e s e t 38 figure 10. bit_clk to sync t i ming diagram 39 figure 1 1 . data setup and hold 40 figure 12. signal rising and falling t i me diagram 40 figure 13. ac-link low power mode t i ming diagram 41 figure 14. a t e t e st mode t i ming diagram 42 11. list of t ables t able 1. digital signal list 8 t able 2. analog signal list 8 t able 3. filtering and v o ltage references 9 t able 4. power signal list of cmi9739 9 t able 5. configuration signals of cmi9739 9 t able 6. s/pdif signals of cmi9739 9 t able 7. mixer functional connections 20 t able 8. mixer registers 22 t able 9. cold reset t i ming parameters 38 t a b l e 1 0 . w a r m r e s e t 38 t able 1 1 . clocks 39 t able 12. data setup and hold t i ming parameters 40 t able 13. signal rising and falling t i mes parameters 41 t able 14. ac-link low power mode t i ming parameters 41 t able 15. a t e t e st mode t i ming parameters 42 revision date: may 2002 v e r s i o n : 1 . 3 7 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 3. pin/signal descriptions 3.1 digit a l i/o these signa ls con nect cmi9739 to its ac?97 co ntroller co un terpart, external crystal, multi-codec selection, and external audio amplifier . t able 1. digital signal list sig n a l name t y p e descrip tio n reset # i ac?97 master h/w reset xt l _ i n i 24.576mhz cry s tal or external 14.318mhz clock source xt l_out o 24.576 mhz cry s tal sy nc i 48 khz fix ed rate sample sy nc bit _ clk o 12.288 mhz serial data clock sda t a_out i serial, time division multiplexed, ac?97 input stream sda t a_in o serial, time division multiplexed, ac? 97 output stream # denotes active low 3.2 analog i/o these sign als con nect cmi9739 to analog sources and sinks, including micro phones and speakers. t able 2. analog signal list sig n a l name t y p e descrip tio n pc-beep i pc speaker input aux_in_l i aux left channel aux_in_r i aux right channel cd_l i cd audio left channel cd_r i cd audio right channel cd_gnd i cd audio analog ground mic1 i desktop microphone input mic2 o second microphone input line_in_l i line in left channel line_in_r i line in right channel line_out _l o line out left channel line_out _r o line out right channel rear_out _l o rear out left channel rear_out _r o rear out right channel lf e_out o low frequency ef fect out channel center_out o center out channel revision date: may 2002 v e r s i o n : 1 . 3 8 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 hp_out _l o earphone left channel (for cmi9739) hp_out _ r o earphone right channel (for cmi9739) line_hp_out _l o line out/ earphone left channel (for CMI9739A) line_hp_out _ r o line out /ear phone right channel (for CMI9739A) 3.3 reference pin this signal provides bias for micphone. t able3. filtering and v o ltage references sig n a l name t y p e descrip tio n v r efout o reference v o ltage out 5ma drive 3.4 power and ground signals t able4. power signal list of cmi9739 sig n a l name t y p e descrip tio n a v d d 1 i analog vdd 5v a v d d 2 i analog vdd 5v a v s s 1 i a n a l o g g n d a v s s 2 i a n a l o g g n d d v d d 1 i digital vdd 3.3v d v d d 2 i digital vdd 3.3v d v s s 1 i d i g i t a l g n d d v s s 2 i d i g i t a l g n d 3.5 configura tion signals t able5. configuration signals of cmi9739 sig n a l name t y p e descrip tio n xt als0 i select 14.318mhz as external clo ck w hen this pin is tied to digital pow er x t a l s 1 i select 14.0mhz as external clock w hen this pin is tied to digital pow er , 12.288mhz w hen to ground. (xt a ls0 has to be tied to ground) x t l s e l i select 24.576mhz cry s tal as clock source w hen is tied to digital pow er , select external clock as source w hen is tied to ground. 3.6 s/pdif signals t able6. s/pdif signals of cmi9739 sig n a l name t y p e descrip tio n spdif in i s/pdif digital audio signal input spdif o o s/pdif digital audio signal output revision date: may 2002 v e r s i o n : 1 . 3 9 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 4. digit a l interf ace 4.1 ac-link all digital au dio streams, optional modem line codec streams, and command/status information intertransmit data over this ac-link. a breakout of the sign als connecting the two is shown in figure 1. figure1. ac ?97 connection to its companion controller xt al_out xt al_in sda t a_in sdt a _out bit_clk reset# sync ac?97 codec digital dc?97 controller 4.2 clocking cmi9739 ge nerates its clock int e rnally from an externally c onnected 24.576 mhz crystal or an oscillator thr ough the x t al_in pin. synchronization with the ac?97 controler is a c hie v ed through the bit_clk pin at 12.288 mhz half the crystal frequency . the beginning of all audio sample packets or audio frames transmitted over ac-link i s synchronize d to the rising edge of the ?sync? signal . ?sync? is driven by the ac ?9 7 controller . data is transmitted on ac-link and on every rising edge of bit_clk. subsequently , it is sample d on the receiving side of ac-link on each immediately followed falling edge of bit_clk. 4.3 resetting there are three types of reset detailed under ?t iming characteristics? ? 1. a cold reset where all cmi9739 logic (registers included) is initialized to its default state 2. a warm reset where the contents of the cmi9739 register set are left unaltered 3. a register reset which only initializes the cmi9739 registers to their default states after signaling a reset t o cmi9739, the ac?97 controller sh ould not att e mpt to pla y or capture audio data until it has sampled a ?codec ready? indicator via register 26h from cmi9739. note ? when the ac-link ? c odec ready? indicator bit (sda t a _ i n slot 0, bit 15) is 1, it means that the ac-link, ac ?97 control, and status registers are in a fully operating state. revision date: may 2002 v e r s i o n : 1 . 3 10 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 4.4 ac-link digit a l serial interf ace prot ocol cmi9739 tra n sits data to the ac'97 c ontroller via a 5-pin digit a l serial ac-link interface , which is a bi-directio nal, fixed rate, serial p c m digital stream. all digital audio streams, commands, a n d status infor m ation are transitted over this point-to-point serial tran smission. t he ac-link processes multiple inputs, output audio strea m s, as well as control register acce sses by a time division co mplex (tdm) scheme . the ac'97 c ontroller synchronizes all ac-link data transmissions.the following data streams are available on cmi9739 ? j sda t a_out t a g 1 output slot (0) j sda t a_in t a g 1 input slot (0) j status (st a t u s addr & da t a ) read port 2 input slots (1,2) j pcm l & r dac play back 2 output slots (3,4) j pcm l & r adc record 2 input slots (3,4) j pcm center/lf e dac play back 2 output slots (6,9) j pcm l-surr/r-surr dac play back 2 output slots (7,8) j line2 dac/hset dac support 96k audio f r ame 2 output slots (10,1 1 ) figure2. ac ?97 standard bi-directional audio frame synchronization of all ac-link data transmissions is pr ocessed by the ac'97 controller . cmi9739 d r ives the serial bit cl ock onto ac-link. the ac'97 controller t hen utilizes a synchronization signal to construct audio frames. fixed at 48 khz, sync is derived b y dividing th e serial bit clock (bit_ c lk). bit_clk, fixed at 12.288 mhz , and can provide necessary clockin g granularity to support 12, 20-bit outgoing and incoming time slots. ac-link seria l data is transmitted on each rising edge of bi t_clk. as t he receiver of ac-link data, cmi9739 for the outg o ing data w hereas ac'97 controller the incomin g , sampling each serial bit on the falling edges of bit_clk. the ac-link protoco l provides a special 16- bit (13-bit is defined w i th 3 re served trailing bit positions) time slot (slo t 0) wherein each bit co nveys a valid tag for it s correspond ing time slot within the current audio frame. a ?1? in a given bit position of slot 0 indica tes that th e revision date: may 2002 v e r s i o n : 1 . 3 11 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 corresponding time slot within the current audio frame has been assig n ed to a data stream, and contains valid data. if a slot is ?tagged? invalid, it should be the source of the data (cmi9 739 for the input strea m , ac'97 controller for the output strea m ) to fill in all bit posit i ons with 0 ? s during the active time of that slot. sync remai n s high for a total duratio n of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is defined as the ?t ag phase?. the remainder of the audio frame where sync is low is defined as the ?data phase?. besides, for power saving, all clock, sync, and data signals can be halted. 4.5 ac-link audio input frame sda t a_in the audio input frame data streams correspon d to the complex bundl es of all digital input dat a targeting the ac 97 controller . as is the case for audio output frame, each ac-link audio input frame consists of 12, 2 0 -bit timeslo t s. slot 0 is a special r e served time slot conta i ning 16-bits which are used for ac-link protocol infrastructure. within slot 0 the f i rst b i t is a g l obal bit (sda t a _in slot 0, b i t 1 5 ) which f l a g s whether cmi9739 is in the ?codecready? state or not. if t he ?codec ready? bi t is a 0, this in dicates that cmi9739 is not ready for normal operation. this con d ition is nor mal following the deassertion of po wer on reset for example , while cmi 9739? s volt age references settle. when the ac-link ?codec ready? indicator bit is a 1 it indicates that th e ac-link and cmi9739 control and status regist ers are in a fully operational state. the ac ?97 controller must further probe the po werdown control/status register (section 6.3) to determine exactly which subsections, if any , are ready . prior to any attempts at putting cmi9739 into op eration the ac ?97 controller should poll the fir s t bit in the au dio input fra m e (sda t a _in slot 0, bit 15) for a n indicat i on that cmi9739 has gone ?codec re ady?. once cmi9739 i s sampled ?codec re ady?8 then the next 12 bit position s sampled by the ac ?97 controller in dicate which of the corre sponding 12 time slots a r e assigned to input data streams, and that they contain valid data. the following diag ram illustrat e s the time slot-based ac-link protocol. revision date: may 2002 v e r s i o n : 1 . 3 12 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 figure3. ac-link audio input frame a new audi o input frame begins with a low to h i gh transitio n of sync. sync is synchronous t o the rising e dge of bit_clk. on th e immediately followed falling edg e of bit_clk, cmi973 9 samples the assertio n of sync. this falling edge marks the t i me when both side s of ac-link are aware of the start of a new audio frame. on the next rising of bit_ clk, cmi9 739 transmits sda t a_in into the first bit position of slot 0 (?codec re ady? bit). each new bit position is presented t o ac-link o n a risin g e dge of bit_ clk, and subsequently sampled b y the ac ?97 controller o n the followi ng falling ed ge of bit_clk. this se quence ensures that da ta transmits and subsequent sample points for both incoming and outgoing data streams are time aligned. figure4. start of an audio input frame the composite stream of sda t a_in i s msb justified (msb firs t) with all non-valid bit positions (fo r assigned an d/or unassig ned time slo t s) filled in with 0 by cmi9739. sda t a_in data is sampled on the falling edges of bit_clk. slot 1: status address port the status p o rt is used t o monitor status for cmi 9739 functio n s includin g , but not limited to, mi xe r settings and power management (refer to section 6.3 of this specification). revision date: may 2002 v e r s i o n : 1 . 3 13 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 the stream of audio inp u t frame slot 1 echoes t he control r egister inde x, for prior reference, a n d for the data to be returned in slot 2. (assuming that slots 1 and 2 had been tagged ?valid? b y cmi9739 during slot 0.) status address port bit allocations: bit 19 reser ved (filled in w i th 0) bit 18 ? 12 control register index (ec ho of register index for w h ich data is being returned) bit 11 ? 0 reser ved (filled in w i th 0? s) the first bit (msb) gene rated by cmi9739 is alw a ys filled in with a 0. th e following 7 bit posit ions transit the a ssociate d control regist er address, and the tra iling 12 b i t po sitions are f i lled in with 0 by cmi9739. slot 2: status data port the status data port delivers 16bit control register read data. bit 19 ? 4 control register read data (filled in by 0 if tagged ?invalid?) bit 3 ? 0 reser ved ( filled in by 0) if slot 2 is tagged invalid by cmi9739, then the entire slot will be filled in with 0. slot 3: pcm record left channel audio input frame slot 3 is the left channel output of cmi9739 input mux and post-adc. cmi9739 adcs are implemented to support 16bit resolution. cmi9739 outputs its adc data (msb first), and fills in any trailing non-valid bit positions by 0 to fill with its 20bit time slot. slot 4: pcm record right channel audio input frame slot 4 is the right channel output of cmi9739 input mux and post-adc. cmi9739 outputs its adc data (msb first), and fills in any trailing non-valid bit positions by 0 to fill in its 20bit time slot . slot 5: optional modem line 1 adc audio input frame slots 5-12 are not used by cmi9739 and are always filled in with 0. revision date: may 2002 v e r s i o n : 1 . 3 14 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 4.6 ac-link audio output frame sda t a_out the audio output frame data streams correspon d to the complex bundles of all digit a l output data targeting the cmi9739 dac inputs, and control re gisters. each audio outp u t frame supports up to 12 to 20bit outgoing data time slots. slot 0 is a specially rese rved time sl ot containin g 16bit that is used for ac-link protocol infrastructure. within slot 0 , the first bit is a global b i t (sda t a _ o ut slot 0, bit 15) which flags the validity for the entire audio frame. if t he ?v alid frame? bit is a 1, this in dicates that the current audio frame contains at least one slot time of valid data. t he next 12 bit positions sampled b y cmi9739 indicate which of the cor r esponding 12 times slo t s conta i n valid data. in this way dat a streams of dif f erent sa mple rates can be transmitted across ac-link at its fixed 48khz audio frame rate. th e following diagram illustrates the time slot based ac-link protocol. figure5 . ac-link audio output frame a new audio output frame begins wit h a low to high transit ion of sync. sync is synchronous to the rising e dge of bit_clk. on th e immediately followed falling edg e of bit_clk, cmi973 9 samples the assertion of sync. thi s following edge marks the time wh en both sides of ac-link are aware of the start of a new audio frame. on the next rising edge of bit_cl k , the ac'9 7 controller tra n smits sda t a_out into the first b i t position o f slot 0 (v alid frame bit). each new bit position is presented to ac-link o n a rising edge of bit_ clk, and s ubsequently sampled b y cmi9739 on the fol l o w ing falling edge of bit_clk. this se que nce ensure s that d a ta transmissio n s and sub s equent sa mple points for both incoming and outgoing da ta streams are time aligned. figure 6. start of an audio output frame sda t a_ out? s composite stream is msb justified (m sb first ) with all non-valid slots? bit position s ac'97 controller . when mono audio sample st reams are sent from the ac'97 controller it is necessary that both left and right sample stream time slots be filled with the same data. revision date: may 2002 v e r s i o n : 1 . 3 15 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 slot 1: command address port the comma nd port is used to control features an d monitor st atus (see audio input frame slots 1 and 2) of t he cmi973 9 functions including, but not limited to, mi xer settings, and powe r management (please refer to the control register section of this specification). the control interface ar chitecture supports up t o 64 16-bit read/write r egisters, ad dressable on even byte boundaries. only the even registers (00h, 02h, etc.) are valid. audio output frame slot 1 transits co ntrol register address, and write/read command in formation to cmi9739. command address port bit allocations ? bit 19 read/w r ite command (1=read, 0=write) bit 18 ? 12 control register index (64 16-bit lo cations,addr essed on even byte boundaries) bit 11 ? 0 reserved (filled in with 0? s) the first bit (msb) sampl ed by cmi9 739 indicate s whether the current control transmission is in a read or a write mode. t he following 7 bit positions transit t he targeted control reg i ster address. the trailing 12 bit positi ons within t he slot are r e served and must be filled in with 0 by the ac ?97 controller . slot 2: command data port the comma nd data port is used to deliver 16bit control register write data in the e v ent that the current command port mode is in a write cycle. (as indicated by slot 1, bit 19) bit 19 ? 4 control register w r ite data (filled in with 0 if current mode is read ) bit 3 ? 0 reserved (filled in with 0) if the current command port mode is in read then the entire sl ot time must be filled in with 0 by th e ac'97 controller . slot 3: pcm play back left channel in a commo n?games compatible" pc, the slot comprises standard pcm (. wav), output samples digitally mixed (by the a c '97 controller or ho st pr ocessor) wit h music synthesis output samples. if a sample st ream of resolution less than 20bit is transmitte d, the ac'9 7 controller must fill in a l l trailing non-valid bit positions by 0 within this time slot. revision date: may 2002 v e r s i o n : 1 . 3 16 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 slot 4: pcm play back right channel audio output frame slot 4 is the co mposite di gital audio rig h t playback stream. in a common ? ga mes compatible" pc, this slo t comprises standard pcm (. wav) output samples digita lly mixed (b y the ac'97 controller or host processor) with music synthe sis output samples. if a sample stre am of resolution less t han 20bit is transmitted, the ac'97 controller must fill in all trailing non-valid bit positions with 0 within this time slot. slot 5: reserved audio output frame slot 5 is rese rved for modem, not used by cmi9739. slot 6: pcm center channel slot 6 carries center data in 6 channel wave output. slot 7: pcm left surround channel slot 7 carries pcm left surround data in 6 channel wave output. slot 8: pcm right surround channel slot 8 carries pcm right surround data in 6 channel wave output. slot 9: pcm low frequency channel slot 9 carries low frequency data in 6 channel wave output. slot 10: pcm alternate left audio output frame slot 10 is not used by cmi9739. slot 1 1 : pcm alternate right audio output frame slot 1 1 is not used by cmi9739. slot 12: reserved audio output frame slot 12 is rese rved for modem, not used by cmi9739. 4.7 ac-link low power mode the cmi973 9 ac-link can be placed in the low power mode by progra m ming register 26h to the appropriate value. both bit_clk an d sda t a_in will be brou ght to, and h e ld at a log i c low voltage level. the ac'97 controller can wake up cmi9739 by providing the appropriate reset signals. revision date: may 2002 v e r s i o n : 1 . 3 17 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 figure 7. ac-link powerdown t i ming bit_clk an d sda t a_i n are transmitted low i mmediately (within the maxi mum specified tim e ) following th e decode of the write to the powerdown register (26h) with pr4. when the ac'9 7 controller driver is at the point where it is ready to program t he ac-link into its low p o wer mode, slots (1 and 2) are assu med to be t he only valid stream in the audio o u tput frame (all sour ces of audio input have been neutralized). the ac'97 controller sho u ld also driv e sync and sda t a_ out low after programmi ng cmi973 9 to this low power mode. w aking up the ac-link once cmi9 739 has halted bit_cl k , there are only two ways to ?wak e up? the ac-link. both methods must be activated by the ac'97 cont roller . the ac-link protocol provides for a ?cold ac'97 rese t?, and a ?w arm ac'97 reset?. the current power down state would ultimately dicta t e which form of reset is a ppropriate. unless a ?co l d? or ?reg i st er? reset (a write to the reset regist er) is performed, wherein t he ac'97 registers are initialized t o their defa u lt values, r egisters are required to keep state during all p o wer down modes. once powered down, re-activation of t h e ac-link via re- assertion of the sync signal must not occur for a minimum of 4 audio frame times following the frame in which the power down wa s triggered. when ac-li n k powers up it indicate s readiness via the codec ready bit (input slot 0, bit 15). cold ac ?9 7 reset ? a cold rese t is ach i eved by assertin g reset# f o r the minimum specified time. by driving reset# low and bit _ clk, sda t a_in will be activated, o r re-activated as the case may be, and all cmi9739 control registers will be initialized to their default power on reset values. note: reset# is an asy n chronous input. revision date: may 2002 v e r s i o n : 1 . 3 18 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 # denotes active low . w a rm ac?9 7 reset ? a warm reset will re-a ctivate the ac-link without alterin g the curre nt cmi9739 register value s . a warm reset is sig n a led by driving sync high for a minimum of 1us in the absence of bit_clk. note: within normal au dio frames, sync is a synchronous input. however , in the absence of bit_clk, sync is treated as an asynchronous input used in the generation of a warm reset to the cmi9739. revision date: may 2002 v e r s i o n : 1 . 3 19 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 5. cmi9739 mixer the cmi973 9 mixer is d e signed according to to the ac?97 specificat ions, capable of managing the playback and recording of all digital and analog audio sources in the pc environment. it includes ? sy stem audio digital pcm input and output for business, gaming, and multimedia applications. ? cd/dvd analog cd/dvd-rom redbook audio with internal connections to codec mixer . ? mono microphone desktop or headset mic, with programmable boost and gain. ? speakerphone system mic & speakers for telephony , dsvd, and video conference. ? stereo line in analog external line level source from consumer audio, video cameras, etc. ? aux/sy n th analog fm or wavetable synthesizer , or other internal sources. t able 7. mixer functional connections s o u r c e f u n c t i o n c o n n e c t i o n pc_beep pc beep pass through from pc beeper output mic1 desktop microphone from mic jack mic2 headset microphone from headset mic jack line_in external audio sources from line in jack cd audio from cd-rom drive cable from cd-rom aux upgrade sy nth or other exter nal sources internal connector pcm out digital audio output from ac ' 97 controller ac-link mix out mix of all sources ac ?97 internal center_out c e n t e r out channel to output jack lf e_out low f r equency ef fect out channel to output jack line_out stereo mix of all sour ces (front channel) to output jack rear_out stereo output of rear (surround) channel to output jack pcm in digital audio input to ac ' 97 controller ac-link output mix support : input mux support : ? s tereo mix of all sources for line _out ? any mono or stereo source ? s tereo output for rear_out ? m ono or stereo mix of all sources 5.1 mixer input the input of cmi9739 mixer is a mux design which of fers th e capability to record audio sources or the outgoin g mix of all sources. t h is design is more ef ficient to implement, compared with an independent input mix. it of fers simple monito ring when a mix is recorded: what you hear is what you get (wyhiwyg). cmi9739 supports the following input sources ? any mono or stereo source ? mono or stereo mix of all sources revision date: may 2002 v e r s i o n : 1 . 3 20 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 5.2 mixer output the mixer generates four distinct outputs: ? a stereo mix of all sources for output to the line_out ? a stereo output of rear (surround) channel for rear_out ? a mono output of center channel for center_out ? a mono output of low frequency ef fect channel for lfe_out revision date: may 2002 v e r s i o n : 1 . 3 21 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 6. register interf ace t able 8. mixer registers reg num n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 00h reset x s e 4 s e 3 s e 2 s e 1 s e 0 i d 9 i d 8 i d 7 i d 6 i d 5 i d 4 i d 3 i d 2 i d 1 i d 0 0 0 0 0 h 02h master v o lume m u t e x x m l 4 m l 3 m l 2 m l 1 m l 0 x x x m r 4 m r 3 m r 2 m r 1 m r 0 8 0 0 0 h 0ah pc_beep volume m u t e x x x x x x x x x x p v 3 p v 2 p v 1 p v 0 x 0 0 0 0 h 0eh mic v o lume m u t e x x x x x x x x boo st x g n 4 g n 3 g n 2 g n 1 g n 0 8008h 10h line-in v o lume m u t e x x g l 4 g l 3 g l 2 g l 1 gl0 x x x g r 4 g r 3 g r 2 g r 1 g r 0 8808h 12h cd v o lume m u t e x x g l 4 g l 3 g l 2 g l 1 gl0 x x x g r 4 g r 3 g r 2 g r 1 g r 0 8808h 16h aux v o lume m u t e x x g l 4 g l 3 g l 2 g l 1 gl0 x x x g r 4 g r 3 g r 2 g r 1 g r 0 8808h 18h pcm out v o l m u t e x x x x x x x x x x x x x x x 8 8 0 8 h 1ah record select x x x x x s l 2 s l 1 s l 0 x x x x x s r 2 s r 1 s r 0 0 0 0 0 h 1ch record gain m u t e x x x g l 3 g l 2 g l 1 g l 0 x x x x g r 3 g r 2 g r 1 g r 0 8000h 20h general purpose x x x x x x x m s lpb k x x x x x x x 0 0 0 0 h 26h pow e rdow n ctrl/stat eap d p r 6 p r 5 p r 4 p r 3 p r 2 p r 1 p r 0 x x x x ref a n l d a c a d c 0 0 0 x h 28h extended audio id i d 1 i d 0 x x rev 1 rev 0 x lda c sda c cda c dsa 1 dsa 0 x spd if d r a x 0 5 c 6 h 2ah extended audio stat/ctrl x x p r k p r j p r i spc v x lda c sda c cda c sps a1 sps a0 x spd if d r a x 3 c 3 0 h 36h center/lf e mute control lf e mute x x x x x x x c mute x x x x x x x 8 0 8 0 h 38h 6ch v o l:l,r surr m u t e x x x x x x x m u t e x x x x x x x 8 0 8 0 h 3ah s/pdif control v x sps r1 sps r0 l c c 6 c c 5 c c 4 c c 3 c c 2 c c 1 c c 0 p r e cop y audi o p r o 2 0 0 0 h 5ah v endor defined control rev 15 rev 14 rev 13 rev 12 rev 11 rev 10 rev 9 rev 8 rev 7 rev 6 rev 5 rev 4 rev 3 rev 2 rev 1 rev 0 0000h 64h v ender define rev 15 rev 14 rev 13 rev 12 rev 11 rev 10 rev 9 rev 8 rev 7 rev 6 rev 5 rev 4 rev 3 rev 2 rev 1 bst sel 0000h 66h v endor defined control rev 15 rev 14 rev 13 rev 12 rev 11 rev 10 rev 9 rev 8 rev 7 rev 6 rev 5 rev 4 rev 3 rev 2 rev 1 rev 0 0000h 68h spdif in0 sp1 5 sp1 4 sp1 3 sp1 2 sp1 1 sp1 0 s p 9 s p 8 s p 7 s p 6 s p 5 s p 4 s p 3 s p 2 s p 1 s p 0 0 0 0 0 h revision date: may 2002 v e r s i o n : 1 . 3 22 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 6ah spdif in1 sp3 1 sp3 0 sp2 9 sp2 8 sp2 7 sp2 6 sp2 5 sp2 4 sp2 3 sp2 2 sp2 1 sp2 0 sp1 9 sp1 8 sp1 7 sp1 6 0000h 6ch spdif f unction control x x x x x x x spd 32 x x x spi2 sdi spi2 f ig_s piv spd ifs spd i_en 0000h 70h gpio setup gpi2 sdi gpit ag x x x x gp1 i/o gp0 i/o x x gpi o1p gpi o0p x x gpi1 en gpi0 en 0000h 72h gpio status x x x x x x gpii 1s gpii 0s x x gpi o1s gpi o0s x x gpo 1 gpo 0 0000h 7ch v endor id1 f 7 f 6 f 5 f 4 f 3 f 2 f 1 f 0 s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 4 3 4 d h 7eh v endor id2 t7 t 6 t5 t 4 t3 t 2 t1 t 0 rev 7 rev 6 rev 5 rev 4 rev 3 rev 2 rev 1 rev 0 4961h revision date: may 2002 v e r s i o n : 1 . 3 23 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 6.1 register descriptions reset register (index 00h) (read only ) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 00h r e s e t x s e 4 s e 3 s e 2 s e 1 s e 0 i d 9 i d 8 i d 7 i d 6 i d 5 i d 4 i d 3 i d 2 i d 1 i d 0 0 0 0 0 h no hardware 3d : se4?se0 = 00000b 16bit adc & dac : id9?id0 = 0000000000b w r iting this register will reset the mixer register . master v o lume registers (index 02h) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 02h m a s t e r v o lu m e mut e x x ml4 m l 3 m l 2 m l 1 m l 0 x x x mr4 mr3 mr2 mr1 mr0 8000h ? each step correspond s to 1.5 db. the msb of the register is the mute b i t. when this bit is set to 1, the level for that channel is set at - ? the volu me control bit per chann el is 5. supp ort for the 6 th bit (msb) of the level is optional. i f it is written by 1 , cmi9739 will interpret that as x1 1 1 1 1 . it will also respond when read with x1 1 1 1 1 rather then 1xxxxx, the value writte n to it. the default value is 8000h, which corresponds to 0db attenuation with mute. mute m x5... m x0 func tion 0 000000 0 db attenuation 0 0 1 1 1 1 1 46.5db a t t e n u a t i o n 0 1 x x x x x 46. 5db at t enuat i o n 1 x x x x x x pc beep v o lume registers (index 0ah) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 0a h pc beep vo l u m e mut e x x x x x x x x x x p v 3 p v 2 p v 1 p v 0 x 0 0 0 0 h ? the msb of the reg i st er is the mut e bit. when t h is bit is set to 1, the lev e l for that ch annel is se t at - revision date: may 2002 v e r s i o n : 1 . 3 24 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 mute pv3 ...pv0 func tion 0 0000 0 db attenuation 0 1 1 1 1 4 5 d b a t t e n u a t i o n 1 x x x x db attenuation analog mixer input gain registers (index 0eh - 18h) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 0eh m i c v o lu m e m u t e x x x x x x x x 2 0 d b x g n 4 g n 3 g n 2 g n 1 g n 0 8 0 0 8 h 10h line in vo l u m e m u t e x x g l 4 g l 3 g l 2 g l 1 g l 0 x x x g r 4 g r 3 g r 2 g r 1 g r 0 8 8 0 8 h 12h c d v o lu m e m u t e x x g l 4 g l 3 g l 2 g l 1 g l 0 x x x g r 4 g r 3 g r 2 g r 1 g r 0 8 8 0 8 h 16h a u x v o lu m e m u t e x x g l 4 g l 3 g l 2 g l 1 g l 0 x x x g r 4 g r 3 g r 2 g r 1 g r 0 8 8 0 8 h 18h pcm out v o l m u t e x x x x x x x x x x x x x x x 8808h ? each step correspon ds to 1.5 db. the msb of the register is the mute bit. when this bit is set to 1, the level for that channel is set at - db. ? register 0 e h (mic v o l u me register) has an extra bit that is for a 20 db boost. when bit 6 is set to 1, the 20 db boost is on. the default value is 8008, which corresponds to 0 db gain with mute on. mute g x4...gx0 func tion 0 00000 12db gain 0 01000 0 db attenuation 0 11111 34.5db attenuation 1 xxxx db attenuation record select control register (index 1ah) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 1a h r e c o rd s e l e c t x x x x x s l 2 s l 1 s l 0 x x x x x s r 2 s r 1 s r 0 0 0 0 0 h revision date: may 2002 v e r s i o n : 1 . 3 25 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 the default value is 0000h, which corresponds to mic in. sr2...sr0 right record source sl2...sl0 left record source 0 m i c 0 m i c 1 cd in (r) 1 cd in (l) 2 n / a 2 n / a 3 aux in (r) 3 aux in (l) 4 line in (r) 4 line in (l) 5 stereo mix (r) 5 stereo mix (l) 6 m o n o m i x 6 m o n o m i x 7 pc beep 7 pc beep ? if sx0-2 are written by 7, it selects record from pc beep channel. it makes pc beep input channel equivlent to phone-in. record gain registers (index 1ch) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 1ch r e c o rd gain m u t e x x x g l 3 g l 2 g l 1 g l 0 x x x x g r 3 g r 2 g r 1 g r 0 8 0 0 0 h ? each step correspond s to 1. 5 db. 22.5db cor r esponds to 0f0fh and 000fh respectively . the msb of the r egister is th e mute bit. when this bit is set to 1, the level for that channe l(s) is set at - db. the default value is 8000h, which corresponds to 0 db gain with mute on. mute g x3... g x0 func tion 0 1111 + 22.5 db gain 0 0000 0 db gain 1 x x x x x db attenuation general purpose register (index 20h) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 20h g e n e ral pu rp o se x x x x x x x m s l p b k x x x x x x x 0 0 0 0 h bit func tion lpbk adc/dac loopback mode ms microphone selection: 0= mic1,1= m ic2 revision date: may 2002 v e r s i o n : 1 . 3 26 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 pow e rdow n control/status register (index 26h) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 26h pow e rdow n ctrl/stat x p r 6 p r 5 pr4 p r 3 p r 2 p r 1 pr0 x x x x ref anl dac adc 000xh ? this read/write register is used to program powerdown states and monitor subsystem readiness. the lower half of this re gister is rea d only status, a 1 indicating that the subsection is ?ready?. rea d y is defined a s the subse c tion is able to perform i n its nominal state. whe n this regist er is written, the bit values that come in on ac-link will have no ef fect on read only bits 0-7. when the ac-link ?codec ready? indicator bit (sda t a _in slot 0, bit 15) is a 1, it indicates that the ac-link and ac ?97 control and statu s registers a r e in a fully o perational st ate. the ac ?97 controller must further probe this powerdown control/status register to determine e x actly which subsections, if any , are ready . bit func tion x reserved ref vref?s up to nominal level anl analog mixers, etc. ready dac dac section ready to accept data adc adc section ready to transmit data these bits are pseudo. default are ready and controlled by prx . b i t f u n c t i o n pr0 pcm in adc?s & input mux pow e rdow n pr1 pcm out dacs pow e rdow n pr2 analog mixer pow erdow n (vref still on) pr3 analog mixer pow erdow n (vref off) pr4 digital interface (ac-lin k) pow erdow n (external clk off) pr5 internal clk disable pr6 hp amp pow erdow n except for pr4, other bits are pseudo. when is set, corresponding bits will be not ready . ex. pr1 =1 causes dac=0. prx x must set the volume to mute!! pr4 when is set, will shut down the aclink. revision date: may 2002 v e r s i o n : 1 . 3 27 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 extended audio id register (index 28h) (read only ) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 2 8 h ex te nde d a udio id i d 1 i d 0 x x re v1 re v0 x ld ac sdac cd ca x x x sp dif dr a x 0 5 c 6 h ? id1,id0 is always ?00?. ? rev[1:0]=1 indicated that cmi9739 is ac?97 rev2.2 compliant. ? sdac=1 indicates pcm surround dac is supported. ? ldac=1 indicates pcm lfe dac is supported. ? cdac=1 indicates pcm center dac is supported. ? spdif=1 indicates spdif is supported. ? dra=1 indicates double rate audio is supported. extended audio status and control register (index 2ah) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 2a h ex te nde d a udio stat/ctrl x x pr k p r j p r i sp cv x lda c sdac cd ac sp sa1 sp sa0 x sp dif dr a x 3 c 3 0 h ? dra=1 enables double-rate audio mode ? spdif=1 enables the s/pdif transmitter , s/pdif defaults to transmitter of f (powerdown) ? spsa[1:0]=00, s/pdif source data assigned to ac-link slots 3&4 ? spsa[1:0]=01, s/pdif source data assigned to ac-link slots 7&8 ? spsa[1:0]=10, s/pdif source data assigned to ac-link slots 6&9 ? spsa[1:0]=1 1, s/pdif source data assigned to ac-link slots 10&1 1 (default) ? bits d6-8 is read only status of the extended audio feature readiness: sdac=1 indicates the pcm surround dacs are ready , cdac=1 means center dacs are ready , ldac=1 means lfe dacs are ready . ? spcv=1 indicates current s/pdif configuration {spsa} is supported ? bits d1 1-13 are read/write controls of the extended audio feature powerdown: prj=1 turns the pcm surround dacs of f, pri=1 center dacs of f, prk=1 lfe dacs of f. ? the default value after cold or warm register r e set for th is register (xxxxh) is all ext ended featu r es disabled (d3-d0=0) an d powered down (d12=1). the feature readiness status sh ould always be accurate (d7=x). these bits are pseudo. when in 2ch and 6ch, these bits are still visible. prx x must set volume to mute revision date: may 2002 v e r s i o n : 1 . 3 28 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 center/lfe channel mute control (index 36h) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 36h center/l fe mute lf e mute x x x x x x x c mute x x x x x x x 8 0 8 0 h ? the d15/d7 of the register are the mute bits. when these bits are set to 1, the level for that channel(s) is set at - surround channel mute control (index 38h) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 38h surround mute l mute x x x x x x x r mute x x x x x x x 8 0 8 0 h ? the d15/d7 of the register are the mu te bits. when these bits are set to 1, the level for that channel(s) is set at - s/pdif output channel status and control (index 3ah) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 3a h s/pdif ctl v x sps r1 sps r0 l c c 6 c c 5 c c 4 c c 3 c c 2 c c 1 c c 0 p r e copy audi o p r o 2 0 0 0 h d 1 0 ? v : v a lidit y , if this bit is set to 1, each s/pdi f subframe should hav e bit 28 ?v alid flag? = 1. this tags both samples as invalid. ? spsr[1:0] is ?10?, and it means sample rate is 48khz. ? l : generation status ? cc[6:0] : category code ? pre: pre-emphasis ? copy : copyright (0: copy inhibited, 1: copy permitted) ? audio : audio mode (0: pcm, 1: ac-3 or other non-pcm data) ? pro : professional or consumer fo rmat (0: consumer, 1: professional) revision date: may 2002 v e r s i o n : 1 . 3 29 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 v endor defined register (index 5a/66h) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 5a h v e ndor de fine d control rev 15 rev 14 rev 13 rev 12 rev 11 rev 10 rev 9 rev 8 rev 7 rev 6 rev 5 rev 4 rev 3 rev 2 rev 1 r e v 0 0 0 0 0 h 66h v e ndor de fine d control rev 15 rev 14 rev 13 rev 12 rev 11 rev 10 rev 9 rev 8 rev 7 rev 6 rev 5 rev 4 rev 3 rev 2 rev 1 r e v 0 0 0 0 0 h ? all of registers are reserved. please do not write any value! multi-channel control register (index 64h) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 64h mix e r control pcb sw p 4 7 r e f ctl clct l x s 2 l ni mix 2 s x x x x x x x x b s t s el 0000h ? pcbsw : controls pcbeep path 0: bypass master volume/mute controls, 1: pc beep controls by master volume/mute ? p47: configures the pin 47 definition 0: as spdifin, 1: as eapd out ? ref ctl: internal vref output for micphone bios 0: no internal vref output, 1: internal vref output enabled ? clctl: center/lfe channel output control 0: no center/lfe output, 1: center/lfe output enabled ? s2lni: line-in/ surround output control 0: chip line_in pins as line-in purpose 1: chip line_in pins as surround output purpose. ? mix2s: analog input pass to surround control 0: off 1: on ? bstsel: mic boost selection 0: for 20db , 1: for 30db revision date: may 2002 v e r s i o n : 1 . 3 30 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 s/pdif-in status register(index 68/6ah) (r/o) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 6 8 h s p d i f i n statu s0 spi s15 spi s14 spi s13 spi s12 spi s1 1 spi s10 spis 9 spi s8 spi s7 spi s6 spi s5 spi s4 spi s3 spi s2 spi s1 spis 0 0000h 6a h s p d i f i n statu s0 spi s31 spi s30 spi s29 spi s28 spi s27 spi s26 spis 25 spi s24 spi s23 spi s22 spi s21 spi s20 spi s19 spi s18 spi s17 spis 16 0000h these registers are read only and indicate spdif-in consumer status bits data. ? spis30-31: reserved ? spis28-29: clock accuracy ? spis24-27: sample frequency 0000: 44.1khz, 0010: 48khz, others: reserved ? spis20-23: channel number ? spis16-19: source number ? spis15 : generation status ? spis8-14 : category code ? spis6-7: mode ? spis3-5: pre-emphasis ? spis2: copyright (0: copy inhibited, 1: copy permitted) ? spis1: audio mode (0: pcm, 1: ac-3 or other non-pcm data) ? spis0: professional or consumer fo rmat (0: consumer, 1: professional) s/pdif function control register(index 6ch) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 6 c h s p d i f func tion control x x x x x x x s p d 32 x x x s p i 2 sdi spi2 f ig_ spi v spd ifs spdi _en 0000h ? spdi_en : s/pdif input function control 0: spdif in disable, 1: spdif in enable revision date: may 2002 v e r s i o n : 1 . 3 31 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 ? spdifs: s/pdif output source 0: s/pdif output data is from controller, 1: s/pdif output data is from adc ? ig_spiv: s/pdif input valid bit processing 0: ignore valid bit, 1: valid bit active ? spi2f: s/pdif input data send to front channel for monitoring 0: front channel is from aclink, 1: front channel if from s/pdif in ? spi2sdi: s/pdif input data send to controller 0 : s/pdif in is not to sdata_in, 1 : s/pdif in is to sdata_in ? spd32: 32bit software support mode for spdif out spdif out is controlled by software using slot3&7 for left channel, slot4&8 for right channel. parts of slot3[19:0], slot4[19:0], slot7[ 19:0] and slot8[19:0] will be selected to form spdif 32bit: ? slot3[19:4]+slot4[19:4] to form one 32bit subframe ? slot7[19:4]+slot8[19:4] to form the following 32bit subframe slot3[7:4] and slot 7[7:4] are for header s l o t [ 4 ] slot[5 ] s l o t [ 6 ] s l o t [ 7 ] h e a d e r _ b 1 0 0 0 h e a d e r _ m 0 0 1 0 h e a d e r _ w 0 1 0 0 spdif 32 bit mapping: 0-3 header ? by slot3[4:7] or slot7[4:7] 4-15 ? slot3[8]? slot3[19] (o r slot7[8]? slot7[19]) 16-31 ? slot4[4]? slot4[19](o r slot8[4]?slot8[19]) revision date: may 2002 v e r s i o n : 1 . 3 32 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 the block diagram of s/pdif in/out: s/pdif output front dac adc s/pdif input 0 mux 1 0 mux 1 0 mux 1 spdifs spi2f slot-3/4 slot-3/4 slot-3 /4 /7 /8 /6 /9 /1 0 / 1 1 spi2sdi ac-link gpio setup and gpio status register(index 70/72h) (r/w) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 70h gpio se tup gpi 2sd i gpi ta g x x x x g p i 1 i/o gpi 0 i/o x x g p i o1p gpi o0p x x g p i 1en gpi0 e n 0 0 0 0 h 72h gpio status x x x x x x gpii1 s gpii 0s x x gpi o1s gpi o0s x x gp o1 gpo 0 0000h ? gpi2sdi: gpio status indication in sdata_in 0: the gpio0/gpio1 status and its valid tag are not indicated in sdata_in. 1: the gpio0/gpio1 status and its valid tag are indicated in sdata_in ? gpitag: 0: gpi tag (slot12) is inactive, 1: gpi tag (slot12) is active when gpi int asserted ? gpio1i/o: gpio1 function control 0: set gpio1 as input pin. revision date: may 2002 v e r s i o n : 1 . 3 33 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 1: set gpio1 as output pin. ? gpio0i/o: gpio0 function control 0: set gpio0 as input pin. 1: set gpio0 as output pin. ? gpio1p: gpio1 interrupt polarity 0: low to high transition (default) 1: high to low transition ? gpio0p: gpio0 interrupt polarity 0: low to high transition (default) 1: high to low transition ? gpi1en: gpio1 interrupt enable (when gpio1 is used as input) 0: disable 1: enable. a transaction which polarity depends on gpio1p will trigger the gpio interrupt in bit0 of sdata_in?s slot 12. software has to confi rm the primitiveness of gpio1 before enabling gpio1?s interrupt. ? gpi0en: gpio0 interrupt enable (when gpio0 is used as input) 0: disable 1: enable. a transaction which polarity depends on gpio0p will trigger the gpio interrupt in bit0 of sdata_in?s slot 12. software has to confi rm the primitiveness of gpio0 before enabling gpio0?s interrupt. ? gpii1s: gpio1 interrupt status . (when gpio1 is used as input) 0: no gpio1 interrupt. 1: gpio1 interrupt. ? gpii0s: gpio0 interrupt status . (when gpio0 is used as input). 0: no gpio0 interrupt. 1: gpio0 interrupt. ? gpio1s: gpio1 input status 0: gpio1 is driven low by external device. 1: gpio1 is driven high by external device. ? gpio0s: gpio0 input status 0: gpio0 is driven low by external device. 1: gpio0 is driven high by external device. ? gpo1: gpio1 output control 0: drive gpio1 low. 1: drive gpio1 high. ? gpo0: gpio0 output control revision date: may 2002 v e r s i o n : 1 . 3 34 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 0: drive gpio0 low. 1: drive gpio0 high. v endor id registers (index 7ch - 7eh) (read only ) r e g n a m e d 1 5 d 1 4 d 1 3 d 1 2 d1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d e f a u l t 7ch v e ndor id1 f 7 f 6 f 5 f 4 f 3 f 2 f 1 f 0 s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 4 3 4 d h 7eh v e ndor id2 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 r e v 7 r e v 6 r e v 5 r e v 4 r e v 3 r e v 2 r e v 1 r e v 0 4961h 7ch : 434dh ascii code : cm 7eh : 4961h ascii code: i a revision date: may 2002 v e r s i o n : 1 . 3 35 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 6.2 pin descriptions cmi9739 pin # signal name pin # signal name 1 d v d d 1 2 5 a v d d 1 2 x t l _ i n 2 6 a v s s 1 3 x t l _ o u t 2 7 v r e f 4 d v s s 1 2 8 v r e f o u t 5 s d a t a _ o u t 2 9 xt a l s 0 6 b i t _ c l k 3 0 xt a l s 1 7 d v s s 2 3 1 hp_out_l 8 s d a t a _ i n 3 2 hp_out_r 9 d v d d 2 3 3 n c 1 0 s y n c 3 4 n c 1 1 r e s e t # 3 5 line_out_l 1 2 p c _ b e e p 3 6 line_out_r 1 3 n c 3 7 n c 1 4 a u x _ l 3 8 a v d d 2 1 5 a u x _ r 3 9 s _ o u t _ l 1 6 n c 4 0 n c 1 7 n c 4 1 s _ o u t _ r 1 8 c d _ l 4 2 a v s s 2 1 9 c d _ g n d 4 3 c e n t e r _ o u t 2 0 c d _ r 4 4 l f e _ o u t 2 1 m i c 1 4 5 h p _ o n / g p i o 0 2 2 m i c 2 4 6 x t l s e l / g p i o 1 2 3 l i n e _ i n _ l 4 7 e a p d / s p d i f i n 2 4 l i n e _ i n _ r 4 8 s p d i f o cmi9739-6ch revision date: may 2002 v e r s i o n : 1 . 3 36 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 CMI9739A pin # signal name pin # signal name 1 d v d d 1 2 5 a v d d 1 2 x t l _ i n 2 6 a v s s 1 3 x t l _ o u t 2 7 v r e f 4 d v s s 1 2 8 v r e f o u t 5 s d a t a _ o u t 2 9 xt a l s 0 6 b i t _ c l k 3 0 xt a l s 1 7 d v s s 2 3 1 line_out_l 8 s d a t a _ i n 3 2 line_out_r 9 d v d d 2 3 3 n c 1 0 s y n c 3 4 n c 1 1 r e s e t # 3 5 line_hp_out_l 1 2 p c _ b e e p 3 6 line_hp_out_r 1 3 n c 3 7 n c 1 4 a u x _ l 3 8 a v d d 2 1 5 a u x _ r 3 9 s _ o u t _ l 1 6 n c 4 0 n c 1 7 n c 4 1 s _ o u t _ r 1 8 c d _ l 4 2 a v s s 2 1 9 c d _ g n d 4 3 c e n t e r _ o u t 2 0 c d _ r 4 4 l f e _ o u t 2 1 m i c 1 4 5 h p _ o n / g p i o 0 2 2 m i c 2 4 6 x t l s e l / g p i o 1 2 3 l i n e _ i n _ l 4 7 e a p d / s p d i f i n 2 4 l i n e _ i n _ r 4 8 s p d i f o CMI9739A-6ch revision date: may 2002 v e r s i o n : 1 . 3 37 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 7. ac- link timing characteristics (t ambient = 25 c, a v dd = 5.0v 5% ,dvdd = 3.3v 5%, a v ss=dvss+0v ; 50pf external load) 7.1 cold reset figure 8. cold reset t i ming diagram t able 9. cold reset t i ming parameters p a r a m e t e r s y m b o l m i n t y p m a x u n i t s reset # active low pulse w i dth t r es_low 1.0 - - us reset # inactive to bit _ clk star tup delay t r st2clk 162.8 - - ns # denotes active low . 7.2 w arm reset figure 9. w a rm reset t able 10. w a rm reset p a r a m e t e r s y m b o l m i n t y p m a x u n i t s sync active high pulse width t r es_high 1.0 1.3 - us sync inactive to bit_clk startup delay t r st2clk 162.8 - - ns revision date: may 2002 v e r s i o n : 1 . 3 38 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 7.3 clocks figure 10. bit_clk to sync t i ming diagram t able 1 1 . clocks p a r a m e t e r s y m b o l m i n t y p m a x u n i t s bit _ clk frequency - 12.288 - mhz bit _ clk period t c lk_period - 81.4 - ns bit _ clk output jitter - - 750 ps bl t _ clk high pulsew i dth (not e 1) t c lk_high 36 40.7 45 ns bit _ clk low pulse w i dth (not e 1) t c lk_low 36 40.7 45 ns sync frequency - 48.0 - khz sync period t s y n c_period - 20.8 - us sync high pulse w i dth t s y n c_high - 1.3 - us sync low _pulse w i dth t s y n c_low - 19.5 - us note: w o rst case duty cycle restricted to 45/55. revision date: may 2002 v e r s i o n : 1 . 3 39 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 7.4 da t a setup and hold (50pf external load) figure 1 1 . data setup and hold t able 12. data setup and hold t i ming parameters p a r a m e t e r s y m b o l m i n t y p m a x u n i t s setup to falling edge of bit _ clk t s etup 10.0 - - ns hold from falling edge of bit _ clk t hold 10.0 - - ns note: setup and hold time parameters for sda t a_in are with respect to the ac ?97 controller . 7.5 signal rising and f a lling times (50pf external load; from 10% to 90% of vdd) figure 12. signal rising and falling t i mes diagram revision date: may 2002 v e r s i o n : 1 . 3 40 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 t able 13. signal rising and falling time parameters p a r a m e t e r s y m b o l m i n t y p m a x u n i t s bit _ clk rising time t r iseclk 2 - 6 ns bit _ clk falling time t f allclk 2 - 6 ns sync rising time t r isesy n c 2 - 6 ns sy nc falling time t f allsy n c 2 - 6 ns sda t a_in rising time t r isedin 2 - 6 ns sda t a_in falling time t f alldin 2 - 6 ns sda t a_out rising time t r isedout 2 - 6 ns sda t a_out falling time t f alldout 2 - 6 ns 7.6 ac-link low power mode timing figure 13. ac-link low power mode t i ming diagram t able 14. ac-link low power mode t i ming parameters p a r a m e t e r s y m b o l m i n t y p m a x u n i t s end of slot 2 to bit _ clk, sda t a_in low t s 2_pdow n - - 1.0 us revision date: may 2002 v e r s i o n : 1 . 3 41 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 7.7 a t e test mode figure 14. a t e t e st mode t i ming diagram t able 15. a t e t e st mode t i ming parameters p a r a m e t e r s y m b o l m i n t y p m a x u n i t s setup to trailing edge of reset # (also app lies to sy nc) t s etup2rst 15.0 - - ns rising edge of reset # to hi-z delay t o f f - - 25.0 ns notes: n all ac-link signals are normally low th rough the trailing edge of reset#. bringing sda t a_ out high for the trailing edge of reset# causes t he ac-link outputs of cmi9739 to go high impedance which is suitable for a t e in circuit testing. o once either of the two test mode s has been entered, cmi9739 mu st be issued anothe r reset# with all ac-link signals low to return to the normal operating mode. # denotes active low . revision date: may 2002 v e r s i o n : 1 . 3 42 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 8. release note v1.0/v1.1 basic v1.2 04/15/2002 1. modify register description. 2. modify pin description. v1.3 05/23/2002 1. correct pin difinition for CMI9739A codec. revision date: may 2002 v e r s i o n : 1 . 3 43 .com .com .com .com 4 .com u datasheet
cm i 9739 integrated multi-channel ac?97 9. references intel, audio codec ?97 component specification, revision 2.2, september , 2000. end of specifications c-media electronics inc. 6f ., 100, sec. 4, civil boulevard, t a ipei, t a iw an 106 r.o.c. tel:886-2-8773-1 100 f a x:886-2-8773-221 1 e-mail ? sales@cmedia.com.tw url ? http://w w w .cmedia.com.tw revision date: may 2002 v e r s i o n : 1 . 3 44 .com .com .com 4 .com u datasheet

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